1. Field of the Invention
The present invention relates to an electro-luminescence (EL) display device, and more particularly, to an electro-luminescence display device that has a reduced number of output channels of a data driving integrated circuit.
2. Discussion of the Related Art
Until recently, display devices generally employed cathode-ray tubes (CRTs) or television monitors. Presently, many efforts are being made to study and develop various types of flat panel display devices, such as liquid crystal display devices (LCDs), field emission displays (FEDs), plasma display panel (PDPs), and electro-luminescence (EL) displays, as substitutions for CRTs because of their lightness, thin profile, and compact size.
In particular, an EL display panel is a self-luminous device and does not need an additional light source to emit light. Accordingly, an EL display panel has a very thin profile. In addition, the EL display panel can operate using a low DC voltage, thereby having low power consumption and fast response time. Further, the EL display panel is an integrated device having wide viewing angle, and high image contrast, such that it has high endurance of external impacts and a wide range of applications.
There are two types of EL display panels, an inorganic EL device, which uses an inorganic compound as a phosphorous material, and an organic EL display device, which uses an organic compound as the phosphorous material. In particular, an organic EL display device includes an electron injection layer, an electron carrier layer, a light-emitting layer, a hole carrier layer and a hole injection layer. When a predetermined voltage is applied between an anode and a cathode, electrons produced from the cathode are moved via the electron injection layer and the electron carrier layer into the light-emitting layer while holes produced from the anode are moved via the hole injection layer and the hole carrier layer into the light-emitting layer. As a result, the light-emitting layer emits light by a recombination of electrons and holes fed from the electron carrier layer and the hole carrier layer.
FIG. 1 is a schematic cross-sectional view of an organic light-emitting cell of an electro-luminescence display panel according to the related art. In FIG. 1, an organic EL device includes an electron injection layer 4, an electron carrier layer 6, a light-emitting layer 8, a hole carrier layer 10, and a hole injection layer 12, which are sequentially disposed between a cathode 2 and an anode 14. The cathode 2 is a metal electrode and the anode 14 is a transparent electrode.
If a voltage is applied between the anode 14 and the cathode 2, electrons produced from the cathode 2 are moved, via the electron injection layer 4 and the electron carrier layer 6, into the light-emitting layer 8 while holes produced from the anode 14 are moved, via the hole injection layer 12 and the hole carrier layer 10, into the light-emitting layer 8. Thus, the electrons and the holes fed from the electron carrier layer 6 and the hole carrier layer 10, respectively, collide and are recombined at the light-emitting layer 8 to generate light. Then, light is emitted, via the transparent electrode (i.e., the anode 14), to an exterior of the EL device to thereby display a picture.
FIG. 2 is a schematic block diagram of an electro-luminescence display device according to the related art. In FIG. 2, an EL display device includes an EL display panel 16 having pixel cells 22 arranged at pixel areas defined by intersections between scan electrode lines SL1 to SLn and data electrode lines DL1 to DLm, a scan driver integrated circuit 18, hereinafter referred to as “scan D-IC”, for driving the scan electrode lines SL1 to SLn, a data driver integrated circuit 20, hereinafter referred to as “data D-IC”, for driving the data electrode lines DL1 to DLm, and a timing controller 28 for controlling driving timings of the scan D-IC 18 and the data D-IC 20.
In addition, each of the pixel cells 22 includes a light-emitting cell OLED connected between a supply voltage source VDD and a ground voltage source GND, and a light-emitting cell driving circuit 30 for driving the light-emitting cell OLED in response to a driving signal from a corresponding one of the data electrode lines DL and a scanning signal from a corresponding one of the scan electrode lines SL. The light-emitting cell driving circuit 30 includes a driving thin film transistor (TFT) DT connected between the supply voltage source VDD and the light-emitting cell OLED, a first switching element TFT T1 connected to the scan electrode line SL and the data electrode line DL, a second switching element TFT T2 connected to the first switching element TFT T1 and the driving TFT DT, a converter TFT MT connected between a node positioned between the first and second switching element TFTs T1 and T2 and the supply voltage source VDD to form a current mirror circuit with respect to the driving TFT DT, thereby converting a current into a voltage, and a storage capacitor Cst connected between a gate terminal of each of the driving TFT DT and the converter TFT MT and the supply voltage source VDD. Herein, the TFT is a p-type electron metal-oxide semiconductor field effect transistor (MOSFET).
A gate terminal of the driving TFT DT is connected to the gate terminal of the converter TFT MT, a source terminal of the driving TFT DT is connected to the supply voltage source VDD, and a drain terminal of the driving TFT DT is connected to the light-emitting cell OLED. A source terminal of the converter TFT MT is connected to the supply voltage source VDD, and a source terminal of the converter TFT MT is connected to a drain terminal of the first switching element TFT T1 and a source terminal of the second switching element TFT T2. A source terminal of the first switching element TFT T1 is connected to the data electrode line DL, and a drain terminal of the first switching element TFT T1 is connected to a source terminal of the second switching element TFT T2. A drain terminal of the second switching element TFT T2 is connected to the gate terminal of the driving TFT DT, the gate terminal of the converter TFT MT and the storage capacitor Cst. A gate terminal of the first switching element TFT T1 and a gate terminal of the second switching element TFT T2 are connected to a respective scan electrode line. Meanwhile, if the converter TFT MT and the driving TFT DT have same characteristics, the converter TFT MT and the driving TFT DT form a current mirror circuit such that a current amount flowing in the converter TFT MT equals to a current amount flowing in the driving TFT DT.
The timing controller 28 generates a data control signal for controlling the data D-IC 20 and a scan control signal for controlling the scan D-IC 18 using synchronizing signals supplied from an external system (e.g. a graphic card). Further, the timing controller 28 applies a data signal from the external system to the data D-IC 20.
The scan D-IC 18 generates scanning pulses SP in response to the scanning control signal from the timing controller 28, and applies the scanning pulses SP to the scan electrode lines SL1 to SLn as shown in FIG. 3 to sequentially drive the scan electrode lines SL1 to SLn.
The data D-IC 20 supplies current signals having a current level or a pulse width responding to data signals to the data electrode lines DL1 to DLm every horizontal period 1H in response to the data control signal from the timing controller 28. In this case, the data D-IC 20 has DLm output channels 21 that are matched with the data electrode lines DL1 to DLm in a relationship of one to one.
The EL display device applies current signals having a current level or a pulse width proportional to an input data to the pixel cells 22. Each of the pixel cells 22 is light-emitted in proportion to an amount of current fed from the data electrode line DL.
In the EL display device according to the related art, the data D-IC 20 and the data electrode lines DL1 to DLm are in an one-to-one matching relationship, i.e., the data D-IC 20 includes m output channels connecting to m date electrode lines DL1 to DLm. Thus, such a data D-IC having m output channels increases fabrication costs and requires more space of accommodating m output channels. As a undesired result, a size of the EL display device becomes larger.